Program

Registration starts Dec 1st, 2pm (until 8pm) at SIST lobby, ShanghaiTech University, local time.

Overview

Time	Tue, 2 Dec	Time	Wed, 3 Dec	Time	Thu, 4 Dec	Time	Fri, 5 Dec
9:00am-12:00pm	Fusion SoC Workshop (SIST 1A-200)	9:30am-9:50am	Opening session (Auditorium)	9:30am-10:30am	Keynote 2 (Auditorium)	9:30am-10:30am	Keynote 3 (Auditorium)
		9:50am-10:50am	Keynote 1 (Auditorium)		Coffee Break (SIST Lobby)		Coffee Break (SIST Lobby)
			Coffee Break (SIST Lobby)	10:50am-12:20pm	Session 3 (SIST 1C101 lec. hall)	10:50am-11:50am	Session 5 (SIST 1C101 lec. hall)
		11:10am-12:20pm	Session 1 (SIST 1C101 lec. hall)			11:50am-12:30pm	PhD forum (SIST 1C101 lec. hall)
2pm-5pm	AMD tutorial (SIST 1A-200)	1:30pm-3:30pm	Journal session 1 (SIST 1C101 lec. hall) / Journal session 2 (SEM 104 lec. hall)	1:30pm-2:50pm / 1:30pm-3:30pm	Session 4 (SEM 104 lec. hall) / Design Competition (SIST 1C101 lec. hall)	1:30pm-3:00pm	Session 6 (SIST 1C101 lec. hall)
			Coffee Break (SIST Lobby)		Coffee Break (SIST Lobby)		Coffee Break (SIST Lobby)
		3:50pm-4:40pm	Session 2 (SIST 1C101 lec. hall)	3:10pm-4:20pm	Special session (SIST 1C101 lec. hall)	3:20pm-3:40pm	Closing (SIST 1C101 lec. hall)
		5:00pm-5:50pm	Poster session (SIST Lobby)		Break (head to The bund 16 pier)
				6pm-9pm	Banquet, best paper & light city tour

AMD Tutorial

AMD Workshop: What’s New in AMD Vitis and Edge AI for Academic

Date & Time: December 2, 2025 | 14:00 – 16:30

Organizer: AMD

Overview: This workshop presents the latest updates in the AMD Vitis software stack and Edge AI solutions for academic research and teaching. Through concise technical talks and a hands-on lab, attendees will learn recent Vitis enhancements, performance best practices in Vitis HLS, practical workflows for deploying AI at the edge. The workshop is aimed at faculty, researchers, students, and developers working on embedded systems, FPGA acceleration, and edge AI.

Agenda

14:00 – 14:30 — Advancing Embedded and System Design with the Evolving Vitis

14:30 – 15:00 — Performance-Driven Innovation in Vitis HLS

15:15 – 16:00 — LLM-Aided Vitis HLS Coding Hands-on Lab

16:00 – 16:30 — AI PC and Edge AI for academic

Main Day 1

Time	Main Day 1: Wednesday, 3rd December
9:30am-9:50am	Opening session (Auditorium)
9:50am-10:50am	Keynote 1 (Chair: Prof. Yajun Ha) Prof. Vaugh Betz, University of Toronto
10:50am-11:10am	Coffee Break
11:10am-12:20pm	Session 1: Accelerator (Chair: Prof. Vincent J. Mooney) - On-device Inference and Training Acceleration of Graph Neural Networks with Quantized Arithmetic. Jose Nunez-Yanez and Olle Hansson. - An Efficient FPGA Accelerator for Learning Image Compression. Shengtao Zhao, Yingchang Mao, Zhaoqing Pan and Qiang Liu. - (Short Paper) Hacking the Pipeline: Enabling Fine-Grain Reconfigurable Acceleration within CPU Cores. Zhengyi Zhang, Sijing Yang, Sichao Chen, Yuan Dai, Wenbo Yin and Lingli Wang. - FRME: An FPGA-Accelerated Event-Based Real-Time Rotational Motion Estimator for SLAM. Runhua Wang, Shen Zhang, Guangyao Yan, Tianhang Liu, Zhiqi Zhou, Shuang Guo, Boyi Wei, Chenyang Shi, Hui Wang and Yajun Ha. Best Paper Candidate - JEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs. Zhiqiang Que, Chang Sun, Sudarshan Paramesvaran, Emyr Clement, Katerina Karakoulaki, Christopher Brown, Lauri A O Laatu, Arianna Cox, Alexander Tapper, Wayne Luk and Maria Spiropulu. Best Paper Candidate Artifacts: Available, Evaluated Functional, Reusable, Results Replicated
12:20pm-13:30pm	Lunch Break
1:30pm-3:30pm	Journal Session 1: Design & Applications (Chair: Prof. Christophe Bobda; Prof. Jeff Goeders) - LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing, Mingyu Shu and Qiang Liu - MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability Enhanced Entropy with 2.2Gbps Throughput, Yuan Zhang and Jiliang Zhang - EMINEM: Efficient FPGA Implementation of Mixed-RadIx NTT Hardware AccElerators for NIST Post-QuantuM Cryptography Falcon, Dilithium, and HAWK, Yazheng Tu and Jiafeng Xie - REATA: An Efficient Vision Transformer Accelerator Featuring a Resource-Optimized Attention Design on Versal ACAP, Wenbo Zhang, Yan Zhang, Yiqi Liu, Lingjie Wu, and Xingtong Hu - HiSpMM:High Performance High Bandwidth Sparse-Dense Matrix Multiplication on HBM-equipped FPGA, Ahmad Sedigh Baroughi, Manoj B. Rajashekar, Akhil R. Baranwal, and Zhenman Fang - HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform, Qilin Hu, Haotian Wang, Chubo Liu, Keqin Li, Kenli Li - Exploring Microscaling MX Minifloat Systolic Arrays on FPGAs, Abdurauf Abdurakhmanov, Suhaib A. Fahmy Journal Session 2: Tools & Architecture (Chair: Prof. Jiafeng Xie) - CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs using a Compute-Dedicated Architecture, Wenheng Ma, Xinhao Yang, Shulin Zeng, Tengxuan Liu, Libo Shen, Hongyi Wang, Shiyao Li, Ke Hong, Zhenhua Zhu, Xuefei Ning, Tsung-Yi Ho, Guohao Dai and Yu Wang - OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs, Ruthwik Reddy Sunketa, Muhammad Ali Farooq, Ganesh Gore, Allen Boston, Pierre-Emmanuel Gaillardon and Aman Arora - OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM, Ali Abbasi, Danesh Germchi, Amin Katani, Mohamed Hassan, Rodolfo Pellizzoni - An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search, Qi Deng, Hao Sun, Yuhao Shu, Jianzhong Xiao, Weixiong Jiang, Hui Wang and Yajun Ha - ISRLUT: Integer-Only FHD Image Super-Resolution based on Neural Lookup Table and Near-Memory Computing, Tianshuo Lu, Jianyang Ding, Bowen Jiang, Huachen Zhang, Wei Xu and Zhilei Chai - PoCo: Extending Task-Parallel HLS Programming with Shared Multi-Producer Multi-Consumer Buffer Support, Akhil Raj Baranwal and Zhenman Fang - TETRIS: A Noval FPGA Virtualization Framework for Fine-grained Sharing via Hierarchical Reconfiguration, Wenbin Teng, Wenqi Lou, Teng Wang, Lei Gong, Chao Wang, Xuehai Zhou - da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs, Chang Sun, Zhiqiang Que, Vladimir Loncar, Wayne Luk, Maria Spiropulu
3:30pm-3:50pm	Coffee Break
3:50pm-4:40pm	Session 2: Application (Chair: Prof. Jose Nunez-Yanez) - CAN't Be Hacked: A Decision Tree-Based Intrusion Detection System for CAN Security. Hyungchul Im, Sangmin Park, Sua Shin and Seongsoo Lee. - PointODE: Lightweight Point Cloud Learning with Neural Ordinary Differential Equations on Edge. Keisuke Sugiura, Mizuki Yasuda and Hiroki Matsutani. - Reconfigurable Multi-Tenant FPGA for Security. Muhammed Kawser Ahmed, Peter Mbua and Christophe Bobda.
5:00pm-5:50pm	Poster Session (Chair: Prof. Jianwang Zhai) - Pairl: Physical-Aware Iterative Retiming with Configurable Latches for FPGA Optimization. Kaixiang Zhu, Jide Zhang, Wai-Shing Luk and Lingli Wang. - HOLMES-HLS: Holistic Optimization and Learning-based Multi-model Exploration System for High-Level Synthesis. Yujie Yan, Guanhua Chen, Ruiyu Lyu, Huizhen Kuang, Kaiwen Zhou, Hao Chen, Lingli Wang and Keren Zhu. - An RRG-aware Pre-routing Arrival Time Prediction Framework based on a Graph AutoEncoder. Yunfei Dai, Kaixiang Zhu, Mingyang Chen, Yuanqi Wang and Lingli Wang. - EdgeCT: A CNN-Transformer Hybrid Accelerator for Edge Vision Tasks on FPGA. Xiang Ye, Qirong Luo, Caiyi Sun, Zhi Qi and Hao Liu. - LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators. Changhong Li, Biswajit Basu and Shreejith Shanker. - BiSRA: Binarized Super-resolution Accelerator with Hierarchical Design. Jiaying Geng, Yongmeng Ye, Zhi Qi and Hao Liu. - Efficient FPGA Resource Graph Learning with Graph Neural Networks for Router Runtime Prediction. Andrew David Gunter and Steve Wilton. - Congestion-aware CAD Optimizations for Routing-constrained FPGAs. Soheil Gholami Shahrouz, Samuel Ho and Vaughn Betz. - Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators. Felix Jentzsch and Marco Platzner. - HHEML: Hybrid Homomorphic Encryption for Privacy-Preserving Machine Learning on Edge. Yu Hin Chan, Hao Yang, Shiyu Shen, Xingyu Fan, Shengzhe Lyu, Patrick S. Y. Hung and Ray C. C. Cheung.

Main Day 2

Time	Main Day 2: Thursday, 4th December
9:30am-10:30am	Keynote 2 (Chair: Prof. Kang Zhao) Prof. Shouyi Yin, Tsinghua University Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends
10:30am-10:50am	Coffee Break
10:50am-12:20pm	Session 3: Design (Chair: Prof. Anca Hangan) - Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs, Lukas Stasytis, Felix Jentzsch, Thomas Preusser, Yaman Umuroglu, Jakoba Petri-Koenig and Zsolt István. Artifacts: Available, Evaluated Functional - High-dimension Linear System Computation based on Efficient Integrated Online Arithmetic, Chifeng Song and He Li. - LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons, Shashank Nag, Alan Bacellar, Zachary Susskind, Anshul Jha, Logan Liberty, Aishwarya Sivakumar, Eugene John, Krishnan Kailas, Priscila Lima, Neeraja J. Yadwadkar, Felipe M. G. França and Lizy K. John. - (Short Paper) LPABMs: Low-Power Approximate Booth Multipliers designed for CNN accelerators, Chenyang Dai, Yuhao Xie, Yuxiang Fu, Han Wang and Bang He. - MPC Solver Hardware Generation Framework with Model-Specific Operation Fusion and Pruning, Zhenyu Wu, Brian Plancher, Ian McInerney, Hayden Kwok-Hay So, Maolin Wang and Kwang-Ting Cheng.
12:20pm-1:30pm	Lunch Break
1:30pm-2:50pm	Session 4: Tools (Chair: Prof. Aman Arora, Prof. Thilo Pionteck) - APDSE: Bridging Exploration and Exploitation in HLS DSE via Adaptive Partitioning with Monte Carlo Tree Search and Bayesian Optimization, Mingbin Liang, Shanshan Wang and Chenglong Xiao. - Design and Exploration of a Parameterized Hybrid Routing Architecture for FPGAs, Yuanqi Wang, Yunfei Dai, Xianfeng Cao, Eric Ren, Xifan Tang, Weijun Qin, Tao Li and Lingli Wang. - HeteroProto: Automated RTL-to-Bitstream Framework for Heterogeneous Multi-FPGA SoC Prototyping, Congwu Zhang, Panyu Wang, Yazhou Wang, Mingyu Chen, Yungang Bao, Yisong Chang and Ke Zhang. - Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy, Xiaoke Wang and Dirk Stroobandt. - An FPGA-Based Low-Latency and Energy-Efficient MIMO Signal Detector with Scalable Architecture and Automated Bit-Width Optimization, Jiaqi Guo, Xiaotian Fan, Xingyu Zhou, Yixiao Cao, Le Liang, Shi Jin, Hao Sun and Yongming Tang. Best Paper Candidate
1:30pm-3:30pm	Design Competition (Chair: Prof. Hao Sun, Prof. Weixiong Jiang) - A Low-Latency and High-Precision Unified Activation and Normalization Accelerator on FPGA, Ao Zhang, Yujun Wei - BF16-ACT: A High-Performance BF16 Activation Function Engine on FPGA, Hepeng Hu, Haodong Zhang, Zhaojie Cheng, and Feng Liang Gluttonous Snake: A FPGA-Based Fully Unified Accelerator for Nonlinear Functions in LLMs, Yutong Jia, Shilin Zhang, Xiangming Guo, Kangping Wang, Chuantao Zheng - Reconfigurable Dataflow Architecture for Multiple Activation Functions on FPGA, Runsen An, Xinling Xie, Hua Yuan, Jun Lin - A Cyclic-Buffered Architecture FPGA Accelerator for ORB Feature Extraction in Stereo Visual SLAM, Te Han, Cheng Liu - A ROS-PYNQ Co-design Framework and Feature Extraction Accelerator for SLAM Acceleration, Ming Xia, Zhao Cang, Haocheng Li, Ziyuan Pu, He Li
2:50pm-3:10pm	Coffee Break
3:10pm-4:20pm	Special Session (Chair: Prof. Chen Zhang) - (Short Paper) FlightOPU: An FPGA Overlay Processor for LLM with HBM-Aware Multi-Die Architecture, Chen Wu, Shaoqiang Lu, Yangbo Wei, Junhong Qian, Jinlong Yan, Zhanfei Chen, Rumin Zhang, Xiao Shi and Lei He. - FPGA Implemented Quantum Approximate Optimization Algorithm for MaxCut Acceleration, Xiyun Zhang, Jiyuan Liu and He Li. - Resource Scheduling and Application Generalization for a Hybrid In-Memory Graph Mining Architecture, Jiahe Zhu, Xueyan Wang and Jianlei Yang. - HC2LHT: An Optimized Architecture for High-Capacity Table Lookup in FPGA Resource-Constrained Scenarios, Weitao Pan, Yonghao Long, Jiahui Hao and Zhiliang Qiu.
6:00pm-9:00pm	Banquet & Best Paper Award

Main Day 3

Time	Main Day 3: Friday, 5th December
9:30am-10:30am	Keynote 3 (Chair: Prof. Miaoqing Huang) Prof. Wei Zhang, Hong Kong University of Science and Technology
10:30am-10:50am	Coffee Break
10:50am-11:50am	Session 5: Architecture (Chair: Prof. Aaron (Yiren) Zhao) - Measuring the Power Constrained Performance of FPGA Architectures in ASAP5 GAA NWFET, Andy Ye. Artifacts: Available, Evaluated Functional, Reusable, Results Replicated - An End-to-End Tool Flow with Intrinsic-Level Kernel Optimization on Versal ACAP, Liyang Dou, Zhe Lin, Kai Shi, Xinya Luan and Kang Zhao. - Cyclo-AMC: Automatic Modulation Classification on Versal utilising Cyclostationary Features, Ruilin Wu, Jingyi Li, Wei Zhang, Xueyuan Liu and Philip Heng Wai Leong. - Fast Multi-tau Correlators on FPGA with Context Switching from and to High-Bandwidth Memory, Abdul Rehman Tareen, Christian Plessl and Tobias Kenter.
11:50am-12:30pm	PhD Forum (Chair: Prof. Jieru Zhao) - An Efficient SRAM Architecture for Transposed and Non-Transposed Memory Access, Can Xiao, Haoran Wu, Xuan Guo, Jianyi Cheng and Yiren Zhao. - BOAMLS: Bayesian Optimization with Attention Mechanism for FPGA Logic Synthesis, Xijun Cheng, Zhongyan Xu, Jicong Fan, Yun Qian, Xiaofeng Gu and Zhiguo Yu. - FLAA: Fused Linear Attention Accelerator for Efficient Inference and Training in Transformers, Zhuoheng Ran, Chong Wu, Renjie Xu, Maolin Che, Ray C.C. Cheung and Hong Yan. - Toward Domain-Aware Energy-Efficient Reconfigurable Architectures, Ensieh Aliagha and Diana Goehringer.
12:30pm-1:30pm	Lunch Break
1:30pm-3:00pm	Session 6: Design & Application (Chair: Prof. Chen Wu) - Power-Efficient FPGA Acceleration of Quantized Neural Networks through Safe Undervolting, Ioanna Souvatzoglou, Konstantinos Argyriou, Grigoris Karaoglanian, Dimitris Agiakatsikas and Mihalis Psarakis. - FlexiHist: Efficient and Accurate Software-driven Histogram Designs for FPGAs. Dragos Lazea, Anca Hangan and Zsolt István. Artifacts: Available, Evaluated Functional - Conflict-Free Block Pipelining for FPGA-Accelerated Stochastic Simulated Bifurcation on Dense Ising Models, Sijie Xu, Qifeng Liao, Honglan Jiang, Jie Han and Siting Liu. Artifacts: Available, Evaluated Functional, Reusable, Results Replicated - Neurocore: A GNN Approach to Configurable IP Core Identification in FPGA Netlists, Dallin Dahl, Keenan Faulkner, James Usevitch and Jeff Goeders. Artifacts: Available, Evaluated Functional, Reusable, Results Replicated - (Short Paper) CITRAP: Configurable Infrastructure Template for Rapid Prototyping on FPGAs, Vitalii Burtsev, Martin Wilhelm, Nandhish Thathanur Rajappa, Ilia Sozutov and Thilo Pionteck.
3:00pm-3:20pm	Coffee Break
3:20pm-3:50pm	Closing