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ATTENTION: Design Contest Final Instructions

Competition Background

The global boom in smart vehicles and autonomous driving has led to increasingly complex algorithms and an explosive growth in data processing demands. These trends have created unprecedented challenges for in-vehicle computing platforms, particularly regarding real-time performance and energy efficiency. Field-Programmable Gate Arrays (FPGAs) offer inherent advantages in parallelism, low latency, customizability, and reconfigurability. As a result, they are emerging as a key enabling technology for deploying autonomous driving algorithms at scale. However, unlocking the full potential of FPGAs, achieving efficient software-hardware co-design, and enabling agile development remain pressing challenges for both industry and academia. This competition focuses on FPGA-based hardware acceleration for complex L5 autonomous driving algorithms and large-scale AI model inference. Its aim is to foster deep integration between cutting-edge algorithms and innovative hardware design, thereby promoting engineering-grade solutions and sustainable technological advancement.

Eligibility & Registration

• Open worldwide to teams from universities, research institutes, and enterprise R&D departments. Industry–academia collaboration is encouraged.
• Each team may have 1–3 members and 1–2 faculty or industry mentors. Each person may join only one team; cross-team participation is not allowed.
• Teams with multi-disciplinary backgrounds (e.g., electronics, integrated circuits, automation, computer science, mechanical engineering, etc.) are encouraged
• Registration is via the China National Undergraduate Embedded Chip and System Design Competition – FPGA Innovation Design Contest (AMD Track) (http://www.fpgachina.cn/). Details of registration link and instructions will be announced later.

Important Dates (All 23:59, AoE):

Phase	Timeline	Notes
Registration	now - Sept 22, 2025	Submit the registration form and project abstract via the official website/email
Preliminary Submission	Nov 7, 2025	Submit technical report, source code, and demonstration video
Preliminary Review	Nov 7 - 14, 2025	Online expert review; shortlist announcement
Finals & On-site Demo	Nov 28 - 30, 2025	Paper presentation, onsite defense, and live demonstration
FPT Conference Presentation and Awarding	Dec 2 - 5, 2025	Oral presentation at FPT and awards ceremony

Tracks and Requirements

The 2025 competition features two main tracks:

1. SLAM Algorithm FPGA Acceleration and Optimization Track: Using the AMD KV260 FPGA platform, design a hardware–software co-optimized acceleration solution for SLAM algorithms on the public KITTI dataset. Evaluation focuses on localization accuracy, acceleration performance, and engineering innovation.
2. FPGA Acceleration for Activation Functions in LLM: Develop an efficient FPGA hardware acceleration design for key activation functions in on-device large language model (LLM) inference, supporting bf16 data type. Evaluation focuses on computational accuracy and throughput.

For detailed descriptions of each track, datasets, evaluation metrics, and scoring criteria, see Appendix 1 (page 4) and Appendix 2 (page 7) in the attachment.

Submission & Evaluation

Preliminary Stage

• Evaluation Method: Double-blind review for fairness.
• Judging Panel: Experts from leading universities, industry, and the FPGA community.
• See the attached track requirements for scoring metrics.

Submission Requirements

• Technical Paper: Papers must be submitted electronically in PDF format, following the IEEE conference double-column format style. Main text 2 pages, plus unlimited appendices. Only the main text of accepted papers will appear in the published FPT’25 proceedings and IEEE Xplore. Accepted paper's team will be invited to the live competition.
• Reproducible Project Package: Including Vitis/Vivado project files, build scripts, test datasets, and GitHub repository link. Winning entries must be open-sourced.
• Demo Video: Up to 5 minutes, showing algorithm functionality, acceleration performance, and deployment demonstration.

Final Stage

• Presentation Format: Each team will be allocated 15 minutes, consisting of a 5-minute oral presentation, a 5-minute live demonstration of their project, and a 5-minute question-and-answer session with the judges.
• Participation: Teams are required to attend the final stage in person. Online participation may be permitted under special circumstances, subject to prior approval by the organizing committee.

Scoring:

• Performance & technical innovation (40%)
• On-site defense & demo (40%)
• Technical Paper (20%)

Awards

Award	Selection Criteria	Prize
1st / 2nd / 3rd Place	Top 3 teams per track	Certificate, FPT proceedings invitation, conference funding
Excellence Award	Finalists not in top 3	Certificate, conference funding

Note: Details of conference funding will be announced later.

Other Notes

• For inquiries, contact us via the official QQ group (1022632722) or email:hao.sun@seu.edu.cn -Please check the oficial website of the China National Undergraduate Embedded Chip and System Design Competition–FPGA Innovation Design Contest (http://www.fpgachina.cn/) for registration and updates.

For the full PDF attachment and appendices, see here: