Keynote
Keynote Speakers
Prof. Vaugh Betz, University of Toronto
Title: Spatial Architectures in the More-than-Moore and Deep Learning Era
Abstract: To meet the stringent energy-efficiency and performance needs of deep learning workloads, minimizing data movement is crucial. This trend plays to the strengths of spatial architectures, including not only FPGAs but also processor arrays with mesh interconnects like the Cerebras Wafer Scale Engine and AMD AI Engine arrays. Spatial architectures have characteristics that make them particularly well-suited to More-than-Moore integration that stacks multiple dice, connects them with interposers, or leverages wafer-scale integration. To explore this broad architecture space, we need to not only update FPGA CAD tools, but to also create entirely new tool flows for spatial processor arrays. In this talk, I will discuss the relative strengths of these spatial platforms vs. GPUs across a range of deep learning applications, outline how the different platforms are exploiting More-than-Moore integration, and give an overview of the tools we are creating to help enable and explore 3D FPGAs, new embedded FPGAs, and spatial processor arrays.
Bio: Dr. Betz is an Professor of Electrical and Computer Engineering at the University of Toronto and a Distinguished Visiting Professor at Cerebras Systems. His research interests cover VLSI design and computer architecture (particularly FPGA and spatial processor array architecture), Computer-Aided Design algorithms, and accelerating deep learning inference.He is the original developer of the VPR FPGA architecture exploration tool and the leader of the open-source Verilog-to-Routing (VTR) project. He co-founded Right Track CAD to commercialize his research; after its acquisition he spent 11 years at Altera, ultimately as Senior Directory of Software Engineering. He is an architect of the Quartus CAD system and the first five generations of the Altera Stratix and Cyclone families. Dr. Betz holds 102 US patents, and has received 18 best or most significant paper awards from top conferences and journals in the field. He is Editor-in-Chief of the ACM Transactions on Reconfigurable Technology and Systems journal and serves on the program committees of several conferences in the CAD and programmable silicon areas. He is an IEEE Fellow, an ACM Fellow, a Fellow of the National Academy of Inventors, a Fellow of the Engineering Institute of Canada, and a Faculty Affiliate of the Vector Institute for Artificial Intelligence.
Prof. Shouyi Yin, Tsinghua University
Title: Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends
Abstract: A reconfigurable ML processor increases hardware flexibility to accommodate various ML algorithms and speeds up processing time while consuming less power. Typically, a reconfigurable ML processor includes multiple reconfiguration hierarchies, such as chip-level, processing element array-level, and processing element-level reconfigurations. Chip-level reconfiguration dynamically adjusts the parallelism of multi-chip systems to minimize computation latency and data access. Processing element array-level reconfiguration changes the dataflow or mapping of the computing engine to fully reuse the on-chip data, reducing the memory access. Processing element-level reconfiguration changes the function of the computing unit, such as computing precision and sparsity processing pattern, to increase the bit-wise hardware utilization. This tutorial explores the fundamental concepts of reconfigurable technology, discusses its applications in both digital and analog ML processors, and prospects for future development trends in reconfigurable technology.
Bio: Shouyi Yin received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2000, 2002, and 2005, respectively. He has worked with Imperial College, London, U.K., as a Research Associate. He is currently a full professor and the dean of School of Integrated Circuits in Tsinghua University. His research interests include reconfigurable computing, AI processors and wafer-scale chips. He has published more than 100 journal papers and more than 50 conference papers. He has served as technical program committee member in the top VLSI and EDA conferences such as ISCA, MICRO, HPCA, DAC, ICCAD, ASPDAC, FPGA and A-SSCC. He is the associate editor of ACM TRETS and Integration, the VLSI journal. He is a fellow of IEEE.
Prof. Wei Zhang, Hong Kong University of Science and Technology
Title: Streamlining FPGA Development: Challenges and Opportunities of Agile Design Flows
Abstract: In today's landscape, the growing diversity and complexity of designs on reconfigurable architectures pose significant challenges for achieving high-efficiency and rapid development workflows. Recently, several agile design flows have been introduced to enhance user interfaces and productivity, such as automatic design frameworks utilizing high-level synthesis and large language models. However, a considerable performance gap remains when compared to manual design. Key questions arise, including the reasons behind the performance overhead and the most promising strategies to address these challenges. In this talk, we will explore the latest advancements in efficient agile design flows and compilers for reconfigurable architectures such as FPGA and AIE, while discussing the trade-offs involved in potential future directions.
Bio: Prof. Wei Zhang is a full professor at the Hong Kong University of Science and Technology. She was an assistant professor in School of Computer Engineering at Nanyang Technological University, Singapore from 2010 to 2013. She has authored and co-authored more than 150 papers in peer-reviewed journals and international conferences, and won the best paper awards in ISVLSI 2009, ICCAD 2017, and ICCAD 2022. Her current research interests include reconfigurable computing, software-hardware co-design, EDA and embedded system security. Prof. Zhang currently serves on several editorial boards, including ACM TRETS, IEEE TCAD, ACM TECS, IEEE TCSAI, etc. She also serves on many conference organization committees and technical program committees, as general chair, TPC chair, Asian representatives, etc.