Program
Overview
| Time | Tue, 2 Dec | Time | Wed, 3 Dec | Time | Thu, 4 Dec | Time | Fri, 5 Dec |
|---|---|---|---|---|---|---|---|
| 9:00am-12:00pm | Workshop | 9:30am-9:50am | Opening session (Auditorium) | 9:30am-10:30am | Keynote 2 (Auditorium) | 9:30am-10:30am | Keynote 3 (Auditorium) |
| 9:50am-10:50am | Keynote 1 (Auditorium) | Coffee Break | Coffee Break | ||||
| Coffee Break | 10:50am-12:20pm | Session 3 | 10:50am-11:50am | Session 5 | |||
| 11:10am-12:20pm | Session 1 (SIST 1C101 lec. hall) | 11:50am-12:30pm | PhD forum | ||||
| 2pm-5pm | AMD tutorial (SIST-1C101) | 1:30pm-3:30pm | Journal session 1 / Journal session 2 | 1:30pm-2:50pm / 1:30pm-3:30pm | Session 4 / Design Competition | 1:30pm-3:30pm | Session 6 |
| Coffee Break | Coffee Break | Coffee Break | |||||
| 3:50pm-4:40pm | Session 2 | 3:10pm-4:20pm | Special session | 3:50pm-4:10pm | Closing | ||
| 5:00pm-5:50pm | Poster session | Break (head to The bund 16 pier & light city tour) | |||||
| 6pm-9pm | Banquet & best paper |
Main Day 1
| Time | Main Day 1: Wednesday, 3rd December |
|---|---|
| 9:30am-9:50am | Opening session (Auditorium) |
| 9:50am-10:50am | Keynote 1 (Chair:) Prof. Vaugh Betz, University of Toronto |
| 10:50am-11:10am | Coffee Break |
| 11:10am-12:20pm | Session 1: Accelerator (Chair:) - On-device Inference and Training Acceleration of Graph Neural Networks with Quantized Arithmetic. Jose Nunez-Yanez and Olle Hansson. - An Efficient FPGA Accelerator for Learning Image Compression. Shengtao Zhao, Yingchang Mao, Zhaoqing Pan and Qiang Liu. - (Short Paper) Hacking the Pipeline: Enabling Fine-Grain Reconfigurable Acceleration within CPU Cores. Zhengyi Zhang, Sijing Yang, Sichao Chen, Yuan Dai, Wenbo Yin and Lingli Wang. - FRME: An FPGA-Accelerated Event-Based Real-Time Rotational Motion Estimator for SLAM. Runhua Wang, Shen Zhang, Guangyao Yan, Tianhang Liu, Zhiqi Zhou, Shuang Guo, Boyi Wei, Chenyang Shi, Hui Wang and Yajun Ha. - JEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs. Zhiqiang Que, Chang Sun, Sudarshan Paramesvaran, Emyr Clement, Katerina Karakoulaki, Christopher Brown, Lauri A O Laatu, Arianna Cox, Alexander Tapper, Wayne Luk and Maria Spiropulu. |
| 12:20pm-13:30pm | Lunch Break |
| 1:30pm-3:30pm | Journal Session 1/2 (Chair:) - MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability Enhanced Entropy with 2.2Gbps Throughput, Zhang, Jiliang - LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing, Liu, Qiang - CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs using a Compute-Dedicated Architecture, Ma, Wenheng - OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs, Sunketa, Ruthwik Reddy - OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM, Abbasi, Ali - HiSpMM:High Performance High Bandwidth Sparse-Dense Matrix Multiplication on HBM-equipped FPGA, Sedigh Baroughi, Ahmad - HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform, Hu, Qilin - An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search, Deng, Qi - Exploring Microscaling MX Minifloat Systolic Arrays on FPGAs, Abdurakhmanov, Abdurauf - AHCA: Agile Design Framework for Hashcat Acceleration based on FPGA, Deng, Liming - ISRLUT: Integer-Only FHD Image Super-Resolution based on Neural Lookup Table and Near-Memory Computing, Lu, Tianshuo - EMINEM: Efficient FPGA Implementation of Mixed-RadIx NTT Hardware AccElerators for NIST Post-QuantuM Cryptography Falcon, Dilithium, and HAWK, Tu, Yazheng - PoCo: Extending Task-Parallel HLS Programming with Shared Multi-Producer Multi-Consumer Buffer Support, Baranwal, Akhil - TETRIS: A Noval FPGA Virtualization Framework for Fine-grained Sharing via Hierarchical Reconfiguration, Teng, Wenbin - REATA: An Efficient Vision Transformer Accelerator Featuring a Resource-Optimized Attention Design on Versal ACAP, Zhang, Yan |
| 3:30pm-3:50pm | Coffee Break |
| 3:50pm-4:40pm | Session 2: Application (Chair:) - CAN't Be Hacked: A Decision Tree-Based Intrusion Detection System for CAN Security. Hyungchul Im, Sangmin Park, Sua Shin and Seongsoo Lee. - PointODE: Lightweight Point Cloud Learning with Neural Ordinary Differential Equations on Edge. Keisuke Sugiura, Mizuki Yasuda and Hiroki Matsutani. - Reconfigurable Multi-Tenant FPGA for Security. Muhammed Kawser Ahmed, Peter Mbua and Christophe Bobda. |
| 5:00pm-5:50pm | Poster Session (Chair:) - Pairl: Physical-Aware Iterative Retiming with Configurable Latches for FPGA Optimization. Kaixiang Zhu, Jide Zhang, Wai-Shing Luk and Lingli Wang. - HOLMES-HLS: Holistic Optimization and Learning-based Multi-model Exploration System for High-Level Synthesis. Yujie Yan, Guanhua Chen, Ruiyu Lyu, Huizhen Kuang, Kaiwen Zhou, Hao Chen, Lingli Wang and Keren Zhu. - ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools. Hanqiu Chen, Andy Wanna and Cong Hao. - An Exploratory Study of Real-Time Simulation on AMD AIEs for Power Electronics. Shouyu Du, Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Yeonho Jeong and Tao Wei. - An RRG-aware Pre-routing Arrival Time Prediction Framework based on a Graph AutoEncoder. Yunfei Dai, Kaixiang Zhu, Mingyang Chen, Yuanqi Wang and Lingli Wang. - EdgeCT: A CNN-Transformer Hybrid Accelerator for Edge Vision Tasks on FPGA. Xiang Ye, Qirong Luo, Caiyi Sun, Zhi Qi and Hao Liu. - LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators. Changhong Li, Biswajit Basu and Shreejith Shanker. - BiSRA: Binarized Super-resolution Accelerator with Hierarchical Design. Jiaying Geng, Yongmeng Ye, Zhi Qi and Hao Liu. - Harnessing Heterogeneous Sparsity and Adaptable Acceleration for Complex-Valued Neural Networks. Zehuan Zhang, Zhengyan Liu, Qiang Liu and Wayne Luk. - Can LLMs Generate RTL Code? A Functional Evaluation Using HLS and NL Prompts. Giordano Lorenzetto, Vanderlei Bonato and Oliver Sinnen. - FPGA Self-Healing for Aging and Variation Mitigation via Live Bitstream Surgery on Commercial 28 nm Devices. Nhlanhla Mavuso, Ezra Thomas and Andre DeHon. - Efficient FPGA Resource Graph Learning with Graph Neural Networks for Router Runtime Prediction. Andrew David Gunter and Steve Wilton. - Congestion-aware CAD Optimizations for Routing-constrained FPGAs. Soheil Gholami Shahrouz, Samuel Ho and Vaughn Betz. - Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators. Felix Jentzsch and Marco Platzner. - HHEML: Hybrid Homomorphic Encryption for Privacy-Preserving Machine Learning on Edge. Yu Hin Chan, Hao Yang, Shiyu Shen, Xingyu Fan, Shengzhe Lyu, Patrick S. Y. Hung and Ray C. C. Cheung. |
Main Day 2
| Time | Main Day 2: Thursday, 4th December |
|---|---|
| 9:30am-10:30am | Keynote 2 (Chair:) Prof. Shouyi Yin, Tsinghua University Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends |
| 10:30am-10:50am | Coffee Break |
| 10:50am-12:20pm | Session 3: Application & Design (Chair:) - Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs, Lukas Stasytis, Felix Jentzsch, Thomas Preusser, Yaman Umuroglu, Jakoba Petri-Koenig and Zsolt István. - High-dimension Linear System Computation based on Efficient Integrated Online Arithmetic, Chifeng Song and He Li. - LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons, Shashank Nag, Alan Bacellar, Zachary Susskind, Anshul Jha, Logan Liberty, Aishwarya Sivakumar, Eugene John, Krishnan Kailas, Priscila Lima, Neeraja J. Yadwadkar, Felipe M. G. França and Lizy K. John. - (Short Paper) LPABMs: Low-Power Approximate Booth Multipliers designed for CNN accelerators, Chenyang Dai, Yuhao Xie, Yuxiang Fu, Han Wang and Bang He. - MPC Solver Hardware Generation Framework with Model-Specific Operation Fusion and Pruning, Zhenyu Wu, Brian Plancher, Ian McInerney, Maolin Wang and Kwang-Ting Cheng. |
| 12:20pm-1:30pm | Lunch Break |
| 1:30pm-2:50pm | Session 4: EDA & Software (Chair:) - APDSE: Bridging Exploration and Exploitation in HLS DSE via Adaptive Partitioning with Monte Carlo Tree Search and Bayesian Optimization, Mingbin Liang, Shanshan Wang and Chenglong Xiao. - Design and Exploration of a Parameterized Hybrid Routing Architecture for FPGAs, Yuanqi Wang, Yunfei Dai, Xianfeng Cao, Eric Ren, Xifan Tang, Weijun Qin, Tao Li and Lingli Wang. - HeteroProto: Automated RTL-to-Bitstream Framework for Heterogeneous Multi-FPGA SoC Prototyping, Congwu Zhang, Panyu Wang, Yazhou Wang, Mingyu Chen, Yungang Bao, Yisong Chang and Ke Zhang. - Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy, Xiaoke Wang and Dirk Stroobandt. - An End-to-End Tool Flow with Intrinsic-Level Kernel Optimization on Versal ACAP, Liyang Dou, Zhe Lin, Kai Shi, Xinya Luan and Kang Zhao. |
| 1:30pm-3:30pm | Design Competition (Chair:) |
| 2:50pm-3:10pm | Coffee Break |
| 3:10pm-4:20pm | Special Session (Chair:) - (Short Paper) FlightOPU: An FPGA Overlay Processor for LLM with HBM-Aware Multi-Die Architecture, Chen Wu, Shaoqiang Lu, Yangbo Wei, Junhong Qian, Jinlong Yan, Zhanfei Chen, Rumin Zhang, Xiao Shi and Lei He. - FPGA Implemented Quantum Approximate Optimization Algorithm for MaxCut Acceleration, Xiyun Zhang, Jiyuan Liu and He Li. - Resource Scheduling and Application Generalization for a Hybrid In-Memory Graph Mining Architecture, Jiahe Zhu, Xueyan Wang and Jianlei Yang. - HC2LHT: An Optimized Architecture for High-Capacity Table Lookup in FPGA Resource-Constrained Scenarios, Weitao Pan, Yonghao Long, Jiahui Hao and Zhiliang Qiu. |
| 6:00pm-9:00pm | Banquet & Best Paper Award |
Main Day 3
| Time | Main Day 3: Friday, 5th December |
|---|---|
| 9:30am-10:30am | Keynote 3 (Chair:) Prof. Wei Zhang, Hong Kong University of Science and Technology |
| 10:30am-10:50am | Coffee Break |
| 10:50am-11:50am | Session 5: Architecture (Chair:) - Measuring the Power Constrained Performance of FPGA Architectures in ASAP5 GAA NWFET, Andy Ye. - An FPGA-Based Low-Latency and Energy-Efficient MIMO Signal Detector with Scalable Architecture and Automated Bit-Width Optimization, Jiaqi Guo, Xiaotian Fan, Xingyu Zhou, Yixiao Cao, Le Liang, Shi Jin, Hao Sun and Yongming Tang. - Cyclo-AMC: Automatic Modulation Classification on Versal utilising Cyclostationary Features, Ruilin Wu, Jingyi Li, Wei Zhang, Xueyuan Liu and Philip Heng Wai Leong. - Fast Multi-tau Correlators on FPGA with Context Switching from and to High-Bandwidth Memory, Abdul Rehman Tareen, Christian Plessl and Tobias Kenter. |
| 11:50am-12:30pm | PhD Forum (Chair:) - BOAMLS: Bayesian Optimization with Attention Mechanism for FPGA Logic Synthesis, Xijun Cheng, Zhongyan Xu, Jicong Fan, Yun Qian, Xiaofeng Gu and Zhiguo Yu. - FLAA: Fused Linear Attention Accelerator for Efficient Inference and Training in Transformers, Zhuoheng Ran, Chong Wu, Renjie Xu, Maolin Che, Ray C.C. Cheung and Hong Yan. - An Efficient SRAM Architecture for Transposed and Non-Transposed Memory Access, Can Xiao, Haoran Wu, Xuan Guo, Jianyi Cheng and Yiren Zhao. - Toward Domain-Aware Energy-Efficient Reconfigurable Architectures, Ensieh Aliagha and Diana Goehringer. - Hardware-Secure Machine Learning, Anthony Etim. |
| 12:30pm-1:30pm | Lunch Break |
| 1:30pm-3:30pm | Session 6: Accelerator & Design (Chair:) - Power-Efficient FPGA Acceleration of Quantized Neural Networks through Safe Undervolting, Ioanna Souvatzoglou, Konstantinos Argyriou, Grigoris Karaoglanian, Dimitris Agiakatsikas and Mihalis Psarakis. - FlexiHist: Efficient and Accurate Software-driven Histogram Designs for FPGAs. Dragos Lazea, Anca Hangan and Zsolt István. - Conflict-Free Block Pipelining for FPGA-Accelerated Stochastic Simulated Bifurcation on Dense Ising Models, Sijie Xu, Qifeng Liao, Honglan Jiang, Jie Han and Siting Liu. - Neurocore: A GNN Approach to Configurable IP Core Identification in FPGA Netlists, Dallin Dahl, Keenan Faulkner, James Usevitch and Jeff Goeders. - (Short Paper) CITRAP: Configurable Infrastructure Template for Rapid Prototyping on FPGAs, Vitalii Burtsev, Martin Wilhelm, Nandhish Thathanur Rajappa, Ilia Sozutov and Thilo Pionteck. |
| 3:30pm-3:50pm | Coffee Break |
| 3:50pm-4:10pm | Closing |
Keynote Speakers
Prof. Vaugh Betz, University of Toronto
Title: Spatial Architectures in the More-than-Moore and Deep Learning Era
Abstract: To meet the stringent energy-efficiency and performance needs of deep learning workloads, minimizing data movement is crucial. This trend plays to the strengths of spatial architectures, including not only FPGAs but also processor arrays with mesh interconnects like the Cerebras Wafer Scale Engine and AMD AI Engine arrays. Spatial architectures have characteristics that make them particularly well-suited to More-than-Moore integration that stacks multiple dice, connects them with interposers, or leverages wafer-scale integration. To explore this broad architecture space, we need to not only update FPGA CAD tools, but to also create entirely new tool flows for spatial processor arrays. In this talk, I will discuss the relative strengths of these spatial platforms vs. GPUs across a range of deep learning applications, outline how the different platforms are exploiting More-than-Moore integration, and give an overview of the tools we are creating to help enable and explore 3D FPGAs, new embedded FPGAs, and spatial processor arrays.
Bio: Dr. Betz is an Professor of Electrical and Computer Engineering at the University of Toronto and a Distinguished Visiting Professor at Cerebras Systems. His research interests cover VLSI design and computer architecture (particularly FPGA and spatial processor array architecture), Computer-Aided Design algorithms, and accelerating deep learning inference.He is the original developer of the VPR FPGA architecture exploration tool and the leader of the open-source Verilog-to-Routing (VTR) project. He co-founded Right Track CAD to commercialize his research; after its acquisition he spent 11 years at Altera, ultimately as Senior Directory of Software Engineering. He is an architect of the Quartus CAD system and the first five generations of the Altera Stratix and Cyclone families. Dr. Betz holds 102 US patents, and has received 18 best or most significant paper awards from top conferences and journals in the field. He is Editor-in-Chief of the ACM Transactions on Reconfigurable Technology and Systems journal and serves on the program committees of several conferences in the CAD and programmable silicon areas. He is an IEEE Fellow, an ACM Fellow, a Fellow of the National Academy of Inventors, a Fellow of the Engineering Institute of Canada, and a Faculty Affiliate of the Vector Institute for Artificial Intelligence.
Prof. Shouyi Yin, Tsinghua University
Title: Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends
Abstract: A reconfigurable ML processor increases hardware flexibility to accommodate various ML algorithms and speeds up processing time while consuming less power. Typically, a reconfigurable ML processor includes multiple reconfiguration hierarchies, such as chip-level, processing element array-level, and processing element-level reconfigurations. Chip-level reconfiguration dynamically adjusts the parallelism of multi-chip systems to minimize computation latency and data access. Processing element array-level reconfiguration changes the dataflow or mapping of the computing engine to fully reuse the on-chip data, reducing the memory access. Processing element-level reconfiguration changes the function of the computing unit, such as computing precision and sparsity processing pattern, to increase the bit-wise hardware utilization. This tutorial explores the fundamental concepts of reconfigurable technology, discusses its applications in both digital and analog ML processors, and prospects for future development trends in reconfigurable technology.
Bio: Shouyi Yin received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2000, 2002, and 2005, respectively. He has worked with Imperial College, London, U.K., as a Research Associate. He is currently a full professor and the dean of School of Integrated Circuits in Tsinghua University. His research interests include reconfigurable computing, AI processors and wafer-scale chips. He has published more than 100 journal papers and more than 50 conference papers. He has served as technical program committee member in the top VLSI and EDA conferences such as ISCA, MICRO, HPCA, DAC, ICCAD, ASPDAC, FPGA and A-SSCC. He is the associate editor of ACM TRETS and Integration, the VLSI journal. He is a fellow of IEEE.
Prof. Wei Zhang, Hong Kong University of Science and Technology
Bio: Prof Zhang received her PhD degree in Electrical Engineering from Princeton University with Wu Prize for research excellence. She joins Hong Kong University of Science and Technology in 2013 and establishes Reconfigurable System Lab. She was an assistant professor in School of Computer Engineering at Nanyang Technological University, Singapore from 2010 to 2013. She is a co-investigator of Singapore-MIT Alliance for Research and Technology and works on low-power electronics. She is a collaborator of ASTAR-UIUC Advanced Digital Sciences Center and works on FPGA acceleration for multimedia applications. Her research interests include reconfigurable system, FPGA-based design, low-power high-performance multicore system, electronic design automation, embedded system and emerging technologies.
Prof Zhang currently serves as the Area Editor of Reconfigurable Computing for ACM Transactions on Embedded Computing Systems. She published more than 50 technical papers in referred international journals and conferences, and authored two book chapters. She receives a best paper award from IEEE Computer Society Annual Symposium on VLSI. She holds two international patents, and one of them is under commercialization. She released three electronic design automation tools. Prof Zhang serves on many organization committees and technical program committees including ISLPED, ASP-DAC, FPT, ARC, etc.